Monday, 20 January 2014

Industry Updates

Viper ASIC Update (Litecoin)

Greetings Miners!
Progress by our engineering partners has been picking up fast and a quick update for the week’s end is as follows:

Engineering Update

  • ASIC design has been more optimized and frozen.
  • ASIC Synthesis & Physical design is going on. Tape out target end of march.
  • Provision for MBIST and boundary scan for DFT has been done.
  • Architecture of Mining Board design has been finalized and design has been started.
  • Sitara ARM AM335x Processor from TI for Host Board has been finalized and design has been initiated.
  • Provision of power consumption & temperature on the LCD display has been incorporated.
  • Eliminated switch from the enclosure. All the input and set up will be done through web pages just like a router. ### Mechanical Update
  • Enclosure material will be of Aluminium.
  • Universal power supply has been identified for 5mh design.
  • 5Mh box will be 1u but much smaller in size ( easy for transportation, likely half of 19” rack).
  • Power figures as of now are looking good
    • 5Mh<=70 watts
    • 25Mh<=300 watts

 You will be given a full warrantee, which is a guarantee from us. Again we do not control the value of individual cryptocurrencies, however, we do guarantee our original shipping deadline, which we are working on beating. If at the worst case scenario shipping is delayed we will work on some sort of repayment.

KNC Neptune Update (Bitcoin)

Neptunes are still very much in the preliminary design phase. As much as the timeline will be reduced significantly in comparison to a standard engineering project at 20nm, if such exists, because this is absolute bleeding edge we want to be absolutely sure what we commit to silicon will ensure a successful product at the end. This initial phase will not be rushed.
That said we have completely re-written and optimised the RTL code. The Jupiter project was very much focused upon safe speed to market and the window of opportunity hashing power presented in this present finite period prior to significant competition. The Neptune project whilst adhering to aspects of the aforementioned must focus upon power consumption as it's primary trait if customers (you guys) will be able to compete successfully over a longer period. We know that we are reaching limits on standard household circuits, we want you to remain competitive w.r.t. the unfolding mining landscape and we are all to well aware that electricity costs will come into focus in the not too distant future.
So where we are now is that we have a working FPGA code and are in the process of testing that and tweaking any further refinements before it's submission.
With respect to the speculation above we sold out of Neptune's last night.

 With respect to Neptune we are where we intended to be at this stage and are still contemplating aspects of the design. Understand that the approach is not the same as that of Jupiter. 28nm was extremely disruptive at the time, of which the effect can plainly be seen. Hashrate was given priority to power consumption, and safety and speed to market even more so, but going forward and acknowledging that power consumption becomes more a critical factor the Neptune has to be created as more a long term solution. We will not skimp or rush the design here. This does not mean I'm indirectly verbalising a delay, so don't go looking for hidden meanings, there aren't any to find, just rest assured I'm stressing we value the integrity of the design more which is why Q1/Q2 was given to ensure that margin is present so we commit the best foot going forward in what is uncharted waters within bleeding edge silicon. We're not rushing the design at the cost of it's ability to function, and function well. The sha-256 implementation is actually relatively simple, but there is still quite a bit we can optimise to remain competitive for you and us.

Viper ASIC Timeline Released

On Monday (13/01/2014) we released an outline of our set roadmap, today as promised we will be releasing a timeline with dates on each aspect of the development process. This shows our commitment to transparency and gives a better idea on what exact stage we are on at all times. As we go through multiple developmental stages in parallel, we will be releasing regular detailed updates on our progress. Our next updates will be consistent developmental updates on what is being worked on and what has been achieved.


Project Start: 16/08/13
Project Finish: 15/07/14
Viper ASIC Miner Project 238 days Tue 16/08/13 Tue 15/07/14
Scrypt Core and Chip Architecture 15 days Mon 06/01/14 Fri 24/01/14
System Architecture 5 days Mon 06/01/14 Fri 10/01/14
FPGA Implementation and Testing 131 days Tue 16/08/13 Fri 14/02/14
ASIC Development 85 days Mon 20/01/14 Fri 16/05/1
Viper Miner Board Design 95 days Mon 13/01/14 Fri 23/05/14
Viper Miner Firmware Development & Testing 118 days Wed 01/01/14 Fri 13/06/14
Mechanical, Thermal & Misc 69 days Mon 13/01/14 Thu 17/04/14
System Assembly & Testing 2 days Mon 16/06/14 Tue 17/06/14
System Integration & Testing 20 days Wed 18/06/14 Tue 15/07/14
User Manual 12 days Fri 18/04/14 Mon 05/05/14
Roadmap (recap):

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